The subject matter disclosed herein relates to the use of simulation to identify potential non-target (undesirable) patterns in a first patterning step of a double-patterning process, and subsequently using that simulation to guide the creation of the cut mask design to be used in a second patterning step. The cut mask design in the second patterning step is designed to remove any non-target (undesirable) patterns.
As integrated circuits (ICs) continue to reduce in size due to technological advances, so too do the ground rules governing designs of these ICs. In some cases, these shrinking ground rules make designing and forming of features in a single mask level unrealistic. Accordingly, double exposure or double patterning techniques have been developed to allow for formation of features according to smaller ground rules. However, conventional rules-based double exposure/double patterning techniques may still fail to properly forecast problems in the masking and exposure processes.